There are many control methods for controlling an output current in a switching mode power supply (SMPS). One control method is a peak current control. FIG. 1A schematically shows a switching mode power supply with a controller AP3708 (Preliminary Datasheet, Rev.1.0, 2008.09, http://www.bcdsemi.com). The controller AP3708 is a primary side controller provided by BCD Semiconductor.
In FIG. 1A, an input signal VIN is applied to a first terminal of a primary winding NP. A second terminal of the primary winding NP is coupled to a transistor Q1, which is controlled to be turned ON and OFF by the controller AP3708. When the transistor Q1 is turned ON, a primary current IP flows through the primary winding NP, which starts building up a magnetic energy. A secondary winding Ns is magnetically coupled to the primary winding NP and includes a secondary diode D1 and a capacitor Co, which has a relatively high capacity to stabilize the variation of a voltage Vo supplying to a load. The polarity (winding sense) of the secondary winding Ns is configured such that the magnetic field produced by the primary current IP (when the transistor Q1 is turned ON) induces a voltage that reverse biases the secondary diode D1; and when the transistor Q1 is turned OFF, the sign of the time derivative of the magnetic field is reversed and a current IS is induced in the secondary winding Ns. A part of the current IS charges the capacitor Co and the rest supplied to the load Ro. The capacitor Co maintains an output current Io flowing to the load by partly discharging while the secondary current IS stops flowing. This is the case when the energy in the magnetic field has been completely discharged.
FIG. 1B shows a prior art peak current control circuit which could be applied in the controller AP3708 or other switching mode power supplies. At the beginning of the switching cycle of the power supply, the transistor Q1 is turned ON, and the primary current IP flowing through the transistor Q1 increases, which causes a voltage VCS across a current sensing resistor RCS to increase. When the voltage VCS reaches a reference signal Vlimit (for example, 0.5V), a comparator 101 provides a comparison signal Comp to a logic circuit 102. Then the logic circuit 102 provides a signal Gate at a pin OUT to turn OFF the transistor Q1, so as to stop the increasing of the primary current IP. The time period when the transistor Q1 is turned ON is defined as an ON time tonp. The relationship between the reference signal Vlimit and the ON time tonp could be expressed as:
                              V          limit                =                              VIN                          L              m                                ×                      t            onp                    ×                      R            CS                                              (        1        )            
wherein Lm represents the inductance of the primary winding NP.
In real world application, when the voltage VCS reaches the reference signal, the transistor Q1 will be turned OFF after a propagation delay. This propagation delay is defined as a shut down delay td. The shut down delay td is usually a fixed value in a given system. Because of the shut down delay td, the transistor Q1 will not be turned OFF immediately when the voltage VCS reaches the reference signal Vlimit.
The value of the voltage VCS is a production of the primary current IP and the resistance of the current sensing resistor RCS. In a given system, the current sensing resistor RCS is constant, which means that the waveform of the primary current IP is similar to the waveform of the voltage VCS despite of their magnitude. FIG. 2 shows waveforms of the voltage VCS under different conditions. Waveform VCS1 has an input signal VIN1. Waveform VCS2 has an input signal VIN2. Persons of ordinary skill in the art should know that waveform VCS1 has a slope of Vlimit×RCS/Lm1, and waveform VCS2 has a slope of VIN2×RCS/Lm2. As seen from FIG. 2, because of different slopes, the error ΔVCS1 and ΔVCS2 caused by the shut down delay td are different. Considering the shut down delay td, a peak current IPK in the primary winding NP could be written as:
                              I          PK                =                                            V              IN                                      L              m                                ⁢                      (                                          t                onp                            +                              t                d                                      )                                              (        2        )            
Substitution of Eq. (1) into Eq. (2) and solution for the input signal VIN yields:
                              I          PK                =                                                            V                IN                                            L                m                                      ⁢                          (                                                t                  onp                                +                                  t                  d                                            )                                =                                                                      V                  limit                                                                      t                    onp                                    ×                                      R                    CS                                                              ⁢                              (                                                      t                    onp                                    +                                      t                    d                                                  )                                      =                                                            V                  limit                                                  R                  CS                                            +                                                                    V                    limit                                                                              t                      onp                                        ×                                          R                      CS                                                                      ×                                  t                  d                                                                                        (        3        )            
Wherein
            V      limit                      t        onp            ×              R        CS              ×      t    d  is the error in the peak current IPK caused by the shut down delay td. From Eq. (2) and Eq. (3), we could find that, even though with a same reference signal Vlimit and a same shut down delay td, the error of the peak current IPK could vary when the input signal VIN or the inductance Lm of the primary winding changes. The errors in the voltage VCS and the peak current IPK caused by the shut down delay td introduce inaccuracy into the output current Io.
The present disclosure provides an improved peak current control circuit for the switching mode power supply and the method thereof to eliminate the error in the peak current caused by the shut down delay.